The present invention relates generally to semiconductor structures, and more specifically, to a semiconductor structure having an embedded single mask adder phase change memory element.
Typically, programming currents required by phase change memories require some aspect of the structure to have a feature size which is sub-lithographically defined in order to maintain a small cell size for the phase change memory element and access circuitry. Some applications, such as fuse devices, have less stringent area requirements. In these applications, it is important to minimize the additional processing costs required to fabricate an embedded memory element into an existing complementary metal oxide semiconductor (CMOS) technology, for example.
FIG. 1 illustrates a typical semiconductor structure. As shown in FIG. 1, a CMOS structure 10 includes a substrate 11 having a borophosphosilicate glass (BPSG) dielectric layer 12 formed thereon. A plurality of conductive contacts 14 (e.g., tungsten) are formed in the BPSG dielectric layer 12 and surrounded by a liner 15 of titanium nitride, for example, used prior to the deposition of the tungsten fill, to form the conductive contacts 14. An access transistor having a gate 16 and spacers 17 adjacent to the sidewalls of the gate 16, and source/drain regions 18 is also provided. Shallow trench isolation (STI) regions 19 are formed within the substrate 11 to provide electrical isolation between the access transistor and other devices. The conductive contacts 14 connect to the source/drain regions 18. A first metal region 19 (M1) is formed on top of each conductive contact 14 within a first dielectric layer 20 and capped with a first cap layer 21. A second dielectric layer 23 is then formed to contain vias 24 and capped with a second cap layer 25. A second metal region 26 (M2) is formed within a third dielectric layer 28, over each via 24 with the vias 24 connecting the first metal regions 19 to the second metal regions 26.